#include <general.h>
#include "opcodes.h"
#include "dynstruct.h"

cpu_instruction dyna_special[64] = {
DYNCPU_SPECIAL_SLL,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_SRL,
DYNCPU_SPECIAL_SRA,
DYNCPU_SPECIAL_SLLV,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_SRLV,
DYNCPU_SPECIAL_SRAV,
DYNCPU_SPECIAL_JR,
DYNCPU_SPECIAL_JALR,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_SYNC,
DYNCPU_SPECIAL_MFHI,
DYNCPU_SPECIAL_MTHI,
DYNCPU_SPECIAL_MFLO,
DYNCPU_SPECIAL_MTLO,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_MULT,
DYNCPU_SPECIAL_MULTU,
DYNCPU_SPECIAL_DIV,
DYNCPU_SPECIAL_DIVU,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_DMULTU,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_DDIVU,
DYNCPU_SPECIAL_ADD,
DYNCPU_SPECIAL_ADDU,
DYNCPU_SPECIAL_SUB,
DYNCPU_SPECIAL_SUBU,
DYNCPU_SPECIAL_AND,
DYNCPU_SPECIAL_OR,
DYNCPU_SPECIAL_XOR,
DYNCPU_SPECIAL_NOR,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_SLT,
DYNCPU_SPECIAL_SLTU,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_DSLL32,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_UNIMPLEMENTED,
DYNCPU_SPECIAL_DSRA32
};

cpu_instruction dyna_regimm[32] =
{
DYNCPU_REGIMM_BLTZ,
DYNCPU_REGIMM_BGEZ,
DYNCPU_REGIMM_BLTZL,
DYNCPU_REGIMM_BGEZL,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_BGEZAL,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED,
DYNCPU_REGIMM_UNIMPLEMENTED
};

cpu_instruction dyna_cop0[64] =
{
DYNCPU_COP0_MOVE,
DYNCPU_COP0_TLBR,
DYNCPU_COP0_TLBWI,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_TLBP,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_ERET,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED,
DYNCPU_COP0_UNIMPLEMENTED
};

cpu_instruction dyna_cop1[32] =
{
DYNCPU_COP1_MFC1,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CFC1,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_MTC1,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CTC1,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_BC,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_S,
DYNCPU_COP1_D,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_W,
DYNCPU_COP1_L,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED
};

cpu_instruction dyna_cop1_s[64] =
{
DYNCPU_COP1_ADDS,
DYNCPU_COP1_SUBS,
DYNCPU_COP1_MULS,
DYNCPU_COP1_DIVS,
DYNCPU_COP1_SQRTS,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_MOVS,
DYNCPU_COP1_NEGS,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_TRUNCWS,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CVTDS,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CVTWS,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS,
DYNCPU_COP1_CCS
};

cpu_instruction dyna_cop1_d[64] =
{
DYNCPU_COP1_ADDD,
DYNCPU_COP1_SUBD,
DYNCPU_COP1_MULD,
DYNCPU_COP1_DIVD,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_MOVD,
DYNCPU_COP1_NEGD,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_TRUNCWD,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CVTSD,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CVTWD,
DYNCPU_COP1_CVTLD,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD,
eCPU_COP1_CCD
};

cpu_instruction dyna_cop1_w[64] =
{
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CVTSW,
DYNCPU_COP1_CVTDW,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW,
DYNCPU_COP1_CCW
};

cpu_instruction dyna_cop1_l[64] =
{
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_UNIMPLEMENTED,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL,
DYNCPU_COP1_CCL
};

cpu_instruction dyna_instr[64] =
{
DYNCPU_SPECIAL,
DYNCPU_REGIMM,
DYNCPU_J,
DYNCPU_JAL,
DYNCPU_BEQ,
DYNCPU_BNE,
DYNCPU_BLEZ,
DYNCPU_BGTZ,
DYNCPU_ADDI,
DYNCPU_ADDIU,
DYNCPU_SLTI,
DYNCPU_SLTIU,
DYNCPU_ANDI,
DYNCPU_ORI,
DYNCPU_XORI,
DYNCPU_LUI,
DYNCPU_COP0,
DYNCPU_COP1,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_BEQL,
DYNCPU_BNEL,
DYNCPU_BLEZL,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_LB,
DYNCPU_LH,
DYNCPU_LWL,
DYNCPU_LW,
DYNCPU_LBU,
DYNCPU_LHU,
DYNCPU_LWR,
DYNCPU_UNIMPLEMENTED,
DYNCPU_SB,
DYNCPU_SH,
DYNCPU_SWL,
DYNCPU_SW,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_SWR,
DYNCPU_COP0_CACHE,
DYNCPU_UNIMPLEMENTED,
DYNCPU_LWC1,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_UNIMPLEMENTED,
DYNCPU_LDC1,
DYNCPU_UNIMPLEMENTED,
DYNCPU_LD,
DYNCPU_UNIMPLEMENTED,
DYNCPU_SWC1,
DYNCPU_UNIMPLEMENTED,
DYNCPU_CODEBLOCK,
DYNCPU_UNIMPLEMENTED,
DYNCPU_SDC1,
DYNCPU_UNIMPLEMENTED,
DYNCPU_SD 
};
